Hackaday

Open Source IDE For FPGAs As QtCreator Learns Verilog

Classic battles: PC vs Mac, Emacs vs Vi, Tastes Great vs Less Filling, and certainly one that we debate around the Hackaday watercooler: command line or IDE? There’s something to be said for using ...
Hackaday

Visualizing Verilog Simulation

You don’t usually think of simulating Verilog code — usually for an FPGA — as a visual process. You write a test script colloquially known as a test bench and run your simulation. You might get some ...
Linux Journal

Icarus Verilog: Open-Source Verilog More Than a Year Later

About 16 months ago, in the February 2001 Linux Journal [see www.linuxjournal.com/article/4428], we reviewed the state of open source in electronic design automation ...
Semiconductor Engineering

Largest High-Quality Verilog Dataset for LLM Fine-Tuning (Univ. of Florida)

A new technical paper titled “VerilogDB: The Largest, Highest-Quality Dataset with a Preprocessing Framework for LLM-based RTL Generation” was published by researchers at the University of Florida.
EDN

Verilog-AMS vs. SPICE view: An SoC verification comparison

Dozens of analog and digital IP blocks are integrated into today’s SoCs. They contain multiple voltage domains that support several modes, like Standby, Low power, Reduced Clock Mode, etc.
Design-Reuse

System Verilog Assertions Simplified

Assertion is a very powerful feature of System Verilog HVL (Hardware Verification Language). Nowadays it is widely adopted and used in most of the design verification projects. This article explains ...
Design-Reuse

System Verilog Macro: A Powerful Feature for Design Verification Projects

For any design verification (DV) project, following best coding practices make life easier for the teammates. On the other hand, bad coding style leads to a lot of issues when the code is reused, or ...