Semiconductor Engineering

New RDL-First PoP Fan-Out Wafer-Level Package Process With Chip-to-Wafer Bonding Technology

How a real chip-last process flow with a chip-to-wafer (C2W) bonding technology can address the RDL-base Interposer PoP challenge. Fan-Out Wafer-Level Interposer Package-on Package (PoP) design has ...
Nasdaq

Akoustis Locks Process Flow for First Wafer-Level-Chip-Scale Package (WLCSP) for XBAW Filters

Charlotte, N.C., Feb. 01, 2021 (GLOBE NEWSWIRE) -- Akoustis Technologies, Inc. (NASDAQ: AKTS) (“Akoustis” or the “Company”), an integrated device manufacturer (IDM) of patented bulk acoustic wave (BAW ...
Semiconductor Engineering

Inspecting Unpatterned Wafers

Unpatterned wafer inspection, which has flown well under the radar for most of the semiconductor industry, is becoming more critical amid the need to find defects earlier in the manufacturing process ...

China's largest chipmaker testing first homegrown immersion DUV litho tool — SMIC takes significant step on road to wafer fab equipment self-sufficiency

SMIC is testing a domestically built immersion DUV lithography system developed by Yuliangsheng and capable of 28nm-class ...
Business Wire

SFN Launches ‘Infrastructure Time Machine’ That Enables Fabs to Reduce Semiconductor Production Times 10 Fold and Increase Net Profit 40-50 Times

NOTTINGHAM, England--(BUSINESS WIRE)--Maximize Chip Act ROI with new transistor technology A new semiconductor technology could be applied at older-generation Fabs, which would enable them to produce ...
Design-Reuse

Synopsys Launches Pre-Wafer Simulation Solution to Reduce Semiconductor Process Development Time

Synopsys, Inc. (NASDAQ: SNPS) today announced a pre-wafer simulation solution to help semiconductor manufacturers reduce process node development time. The new solution provides a comprehensive ...
ExtremeTech

TSMC Announces New System-on-Wafer Process With 3D-Stacking

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pv magazine International

Improving diamond wire sawing to reduce kerf loss in solar wafer production

Researches in China have sought to assess how lateral vibration in diamond wire sawing can increase kerf losses in solar wafer manufacturing and have developed a predictive model than can reportedly ...
Nasdaq

ACM Research Highlights Availability of Portfolio of Wafer-Level Packaging Processing Equipment for OSAT Customers

Extensive Array of Back-End and Advanced Packaging Wet Wafer Process Equipment Leverages ACM’s Experience to Address Emerging Requirements for Wafer-Level Packaging FREMONT, Calif., Oct. 15, 2020 ...
Business Wire

The New Stratus 200 and Stratus 300 Provides Highest Throughput Electrodeposition System with Maximum Wafer Yield

BILLERICA, Mass.--(BUSINESS WIRE)--July 10, 2006--NEXX Systems, a leading provider of processing equipment for advanced wafer level packaging applications, is pleased to introduce the Stratus 200 and ...
Yahoo Finance

Akoustis Locks Process Flow for First Wafer-Level-Chip-Scale Package (WLCSP) for XBAW Filters

The first WLCSP device is expected to be technology qualified later this quarter with production release expected in the June 2021 quarter. The new package offers a significantly smaller filter ...