TechRepublic

Design and simulation of 16 Bit UART Serial Communication Module Based on VHDL

In this paper the authors describe the design of UART (Universal Asynchronous Receiver Transmitter) based on VHDL. As UART is consider as a low speed, low cost data exchange between computer and ...
Elektor Magazine

Mastering FPGA Chip Design with Kevin Hubbard, Elektor Engineering Insights #56

Learn real-world strategies about FPGA Chip Design, Join Elektor Engineering Insights on Sept 24 at 16:00 CEST with Kevin ...
New Electronics

Faster FPGA verification

Launched in 2015, and used by about 20% of all VHDL FPGA designers, UVVM is one of the fastest growing verification methodologies in the EDA industry. Today, design verification accounts for more than ...
Design-Reuse

Capturing a UART Design in MyHDL & Testing It in an FPGA

The universal asynchronous receiver/transmitter (UART) is an old friend to embedded systems engineers. It's probably the first communications protocol that we learn in college. In this article, we ...
Design-Reuse

Modem qpsk vhdl are verilog code IP Listing

The High Data Rate Demodulator IP core can demodulate BPSK, QPSK, offset-QPSK (OQPSK), 8PSK and 16QAM modulation schemes, all to a high performance level and at high symbol rates. The demodulator ...