EDN

How to Read Data Sheets: Logic Timing (Part 3, Flip-Flops)

The JK flip-flop augments the behavior of the SR flip-flop (J = Set, K = Reset) by interpreting the J = K = 1 condition as a “flip” or toggle command. In my previous column, we introduced latches and ...
Electronic Design

Make A Dual ECL Latch Function As A Dual R-S Flip-Flop

The MC1030 is a clocked dual D-type latch. Any change in the D input will be reflected at the output while the clock is low. The outputs are latched on the clock's ...
Embedded

Metastability and Firmware

Metastability is not just a social disease. It could hamper your software's ability to read good data from hardware. Last month I discussed the general problem of making software that reads ...
Semiconductor Engineering

Efficacy of Transistor Interleaving in DICE Flip-Flops at a 22 nm FD SOI Technology Node

Researchers present 3 DICE IFF designs with transistor interleaving, the CnRx construct, and the guard gate technique at the 22 nm FD SOI technology node. April 25th, 2022 - By: Technical Paper Link ...