EDN

ARC recodes for denser instructions

ARC International has developed a more compact instruction set for the next generation of its 32bit configurable processor to let it improve code density to the level offered by compressed formats ...
Design-Reuse

MIPS, ARC look to compress instruction code

LONDON — MIPS Technologies Inc. and ARC International plc, leading examples of companies that license their intellectual property rather than ship it in their own silicon, are set to make ...
EDN

ARC instruction set

ARC's Tangent-core processor is unique among microcontrollers, but companies are starting to move their microcontroller offerings in Tangent's direction. The ARC core provides 30 base instructions, ...
Design-Reuse

ARC introduces 16/32-bit instruction set architecture to reduce memory requirements by up to 30 per cent

ARC's configurable processor adds the ability to run both 16 and 32-bit instructions on a 32-bit architecture, allowing designers to reduce memory requirements by up to 30%, resulting in both lower ...
Electronics Weekly

ARC mixes up instruction set for cores

ARC Cores has announced an instruction set architecture (ISA) that it claims allows designers to mix 16 and 32-bit instructions on its 32-bit user-configurable processor. The main features of the ...